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Data Sheet No. PD60219
IR2161(S)
HALOGEN CONVERTOR CONTROL IC
Features
* Intelligent half-bridge driver * Auto Resetting Short Circuit Protection * Auto Resetting Overload Protection * Externally Triggerable Latching Shutdown * Latching Overtemperature Protection * Frequency Modulation "dither" (for lower EMI) * Micropower Startup (<300 A) * Phase Cut dimmable for leading / trailing edge * Output Voltage Shift Compensation. * Real Softstart * Adaptive Dead Time * Small 8 Pin DIP/SOIC Package
Packages
8-Lead PDIP IR2161
8-Lead SOIC IR2161S
Description
The IR2161 is a dedicated Intelligent Half bridge Driver IC for a Halogen convertor (electronic transformer). It includes all necessary protection features and also allows the Convertor to be dimmed externally with a standard phase cut dimmer with both leading or trailing edge types. This IC provides the advantage of reduced thermal stress in the lamp due to softstart. There is also compensation of the output voltage for load regulation. It enables the convertor to operate with extremely low harmonic distortion over the full range of loads. The IR2161 includes adaptive deadtime to allow cool running MOSFETs and improves the EMI behaviour due to frequency modulation (dither). All the features are integrated in a small 8 pin DIP/SOIC package to allow for a size reduction in the next generation of convertors.
Typical Connections
RD RS CD DS D1 LF CVCC1 COM D2 VCC DCP2 DCP1 DB Q1 R1 C1
1
8
VB
CSNUB
IR2161
2 3 4
AC LINE INPUT
CVCC2 CLF VZ CSD CS
7 HO 6 5
VS LO CB T1
Q2
C3
C4
D3
D4 RL CSD CCS RCS R2 C2
12VAC OUTPUT
Note: Throughout this data sheet "convertor" is spelled in accordance with standard IEC 61047 "DC or AC supplied convertors for filament lamps - Performance requirements".
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Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.
Symbol
VB VS VHO VLO IOMAX VCSDMAX VCS ICS ICC dV/dt PD RthJA TJ TS TL
Definition
High side floating supply voltage High side floating supply offset voltage High side floating output voltage Low side output voltage Maximum allowable output current (HO,LO) due to external power transistor miller effect CSD pin voltage Current sense pin voltage Current sense pin current Supply current (Note 1) Allowable offset voltage slew rate Maximum power dissipation @ TA +25C PD = (TJMAX-TA)/RthJA Thermal resistance, junction to ambient Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) (8 Lead DIP) (8 Lead SOIC) (8 Lead DIP) (8 Lead SOIC)
Min.
-0.3 VB - 25 VS - 0.3 -0.3 -500 -0.3 -0.3 -5 -20 -50 -- -- -- -- -55 -55 --
Max.
625 VB + 0.3 VB + 0.3 VCC + 0.3 500 VCC + 0.3 VCC + 0.3 5 20 50 1 0.625 125 200 150 150 300
Units
V
mA
V mA V/ns W C/W
C
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions.
Symbol
VBS VBSMIN VS VCC ICC CSD ICS TJ Note 1:
Definition
High side floating supply voltage Minimum required VBS voltage for proper HO functionality Steady state high-side floating supply offset voltage Supply voltage Supply current CSD pin external capacitor Current sense pin current Junction temperature
Min.
VCC - 0.7 -- -1 VCCUV+ (Note 2) 47 -1 -25
Max.
VCLAMP 4 600 VCLAMP 10 -- 1 125
Units
V
mA nF mA C
Note 2:
This IC contains a zener clamp structure between the chip VCC and COM which has a nominal breakdown voltage of 15.6V. Please note that this supply pin should not be driven by a DC, low impedance power source greater than the VCLAMP specified in the Electrical Characteristics section. Enough current should be supplied into the VCC pin to keep the internal 15.6V zener clamp diode on this pin regulating its voltage, VCLAMP.
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IR2161(S)
Electrical Characteristics
VCC = VBS = VBIAS = 14V, +/- 0.25V, VCSD = 5.0V, CLO =CHO = 1000 pF, and TA = 25C unless otherwise specified.
Supply Characteristics
Symbol Definition
VCCUV+ VCCUVVCCUVLIQCCUV ICCFLT ICCLF ICCHF VCLAMP VCC supply undervoltage positive going threshold VCC supply undervoltage negative going threshold VCC supply softstart reset negative going threshold UVLO mode quiescent current Fault-mode quiescent current VCC current (low frequency) VCC current (high frequency) VCC zener clamp voltage
Min.
10.8 9.2 -- -- -- -- -- 14.5
Typ.
11.8 10.2 -- -- -- 2 4.1 15.5
Max.
12.8 11.2 5.5 300 2 -- -- 16.5
Units Test Conditions
VCC rising from 0V V VCC falling from 14V VCC - VCCUV- (-2V) A mA V VCC = 11V CS=8V, VCSD=0V VCC=14V,VCSD=5.2V VCC=14V,VCSD=0V ICC = 5mA
Floating Supply Characteristics
Symbol Definition
IBSHF IBSLF ILEAK VBS high frequency supply current VBS low frequency supply current Offset supply leakage current
Min.
-- -- --
Typ.
-- -- --
Max.
3.4 1 50
Units Test Conditions
VCC=14V,VBS=14V, VCSD=0V mA A VCC=14V,VBS=14V, VCSD=5.2V VB = VS = 600V
Voltage Compensation Characteristics (Run Mode)
Symbol Definition Min.
-- --
Typ.
0 5.5
Max.
-- --
Units Test Conditions
V V VCS = 0V VCS = 0.4V
VCSD (min) Min CSD voltage (in Run Mode) VCSD (max) Max CSD voltage (in Run Mode)
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Electrical Characteristics (cont'd)
VCC = VBS = VBIAS = 14V, +/- 0.25V, VCSD = 5.0V, CLO =CHO = 1000 pF, and TA = 25C unless otherwise specified.
Shutdown Circuit Characteristics
Symbol
VCSOL VCSSC IOL ISC IRESET VCSLATCH TCSLATCH VCSDOL VCSDSD
Definition
Overload threshold (CS PID) CSD short circuit threshold (CS PID) CSD overload charging current CSD short circuit charging current CSD shutdown reset current Latched shutdown threshold Latched shutdown delay Begin fault timing Positive going threshold for oscillator shutdown Negative going threshold for oscillator restart
Min.
0.46 1
Typ.
0.54 1.2 9.7 104 0.65 9 1 4.5 12 2.7
Max.
0.63 1.4 12.0 125 1
Units
V
Test Conditions
--
84 0.3
uA V sec
VCS=0.8V,VCSD=7V VCS=1.5V,VCSD=7V VCSD=14V, Note 3 VCS>VCSLATCH VCS>VCSOL VCS > VCSOL
-- -- -- --
-- -- --
V
VCSDRS
--
Thermal Shutdown Characteristics
Symbol Definition
TSD Latched over temperature limit
Min. -- Min.
-- -- -- -- --
Typ.
135
Max. -- Max.
-- -- -- -- --
Units
o
Test Conditions
C
Oscillator Characteristics
Symbol
f(min) f(max) D DTLO(max) DTHO(max)
Definition
Minimum oscillator frequency Maximum oscillator frequency in RUN mode Oscillator duty cycle Maximum LO output deadtime (run mode default) Maximum HO output deadtime (run mode default)
Typ.
33 62 50 1.2 1.5
Units Test Conditions
kHz % sec VCSD = 5.3V VCSD = 0V
no reset from ADT
Adaptive Dead-Time System Characteristics
Symbol Definition
DTLO(min) DTHO(min) Minimum LO output deadtime Minimum HO output deadtime
Min.
-- --
Typ.
-- --
Max.
300 500
Units
sec
Test Conditions
Minimum propagation delay from ADT to output drivers
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ADVANCE DATA
IR2161(S)
Electrical Characteristics (cont.)
VCC = VBS = VBIAS = 14V, +/- 0.25V, VCSD = 5.0V, CLO =CHO = 1000 pF, and TA = 25C unless otherwise specified.
Soft Start Characteristics
Symbol Definition
ISS fSS Soft start CSD charge current Soft start frequency
Min. -- --
Typ.
0.6 130
Max. -- --
Units
mA kHz
Test Conditions
VCC>VCCUV+
Gate Driver Output Characteristics
Symbol
VLO=LOW
Definition
Min.
-- -- -- -- -- -- -- --
Typ.
100 100 100 100 110 55 300 400
Max.
-- -- -- -- 200 150 -- --
Units
Test Conditions
VCSD = 0V VCSD =0V
VLO - VCOM difference between LO output voltage and COM when LO is low VHO=LOW VHO - VS difference between HO output voltage and VS when HO is low VLO=HIGH VCC - VLO difference between VCC and LO output voltage when LO is high VHO=HIGH VB - VHO difference between VB and HO output voltage when HO is high tRISE Turn-on rise time tFALL Turn-off fall time IO+ HO, LO source current IOHO, LO sink current
mV
VCSD = 0V VCSD = 0V
ns mA
CHO=CLO=1nF
Lead Definitions
Symbol
VCC COM CSD CS LO VS HO VB
Lead Assignments
1 8
VB
Description
Supply voltage IC power and signal ground Shutdown timing and compensation capacitor Current sensing input Low-side gate driver output High-side floating return High side gate driver output High side gate driver floating supply
VCC COM CSD CS
IR2161
2 3 4
7 HO 6 5
VS LO
* Recommended value for CSD is 100nF (all performance data relates to this value) NOTE: The recommended value for RL is 1K Ohm and CCS is 1nF.
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IR2161(S)
ADVANCE DATA
Power Turned On
VCC < 5.5V (VCCUVL-) (Power Turned Off)
UVLO Mode
1/
-Bridge Off IQCC 300 A
2
VCC < 5.5V (VCCUVL-) (Power Turned Off)
STANDBY Mode
1/ 2 -Bridge Off IQCC 300 A Oscillator Off
VCC > 11.5V(VCCUV+) T J <135oC (T ) jmax Oscillator On
Oscillator Off CSD = 0V VCC > 11.5V (VCCUV+) T J <135oC (T ) jmax Oscillator On
FAULT Mode
1/ 2 -Bridge Off Oscillator Off
VCC < 9.5V (Phase Cut Dimming)
SOFTSTART Mode
1/ 2-
Fault Detected (Vpk at VCS > 0.5V)
T J <135oC (T ) jmax (Over-Temperature)
Bridge On
Initial frequency 120kHz CSD charged from Isource Frequency ramps down to f(min)
VCSD > 5.2V (End of SOFTSTART Mode) CSD switched to Comp function
VCC < 9.5V (Phase Cut Dimming)
RUN Mode
Voltage compensation active CSD varies between VCSD (min) = 0 for f(min) to VCSD(max) = 5.5V for f(max)
Fault Detected (Vpk at VCS > 7.5V) (VSCLATCH) o T J <135 C (Tjmax) (Over-Temperature) CSD switched to run mode
Auto-Restart Timeout (VCSD < 2.5V) (VCSDRS) CSD switched to run mode
Fault Detected (Vpk at VCS > 0.5V) CSD switched to Shutdown Circuit CSD discharged to 0V Frequency defaults to f(min)
SHUTDOWN Mode
1/ 2
Fault Timing Mode
1/ 2 - Bridge On Fault Confirmed Delay Fault Removed CSD initialized to 4V (VCSDOL) (VCSD > 12V) VCS >0.5V(VCSOL)=Overload:CSD slow charge (Vpk at VCS < 0.5V) CSD is slowly (VCSDSD) (VCSDOL) discharged to 2.5V VCS > 1.2V (VCSSC) = Short Circuit : CSD (VCSDRS) fast charge
-Bridge Off
CSD is slowly discharged
NOTE: If the IR2161 die temperature exceeds 130C at any time the system will enter FAULT Mode. At a typical frequency of 40kHz, the die temperature is approximately 12oC above the ambient air temperature
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IR2161(S)
Block Diagram
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IR2161(S)
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Halogen Convertor Controller Functional Description
Under-voltage Lock-Out Mode (UVLO)
The under-voltage lockout mode (UVLO) is defined as the state the IC is in when VCC is below the turn-on threshold. To identify the different modes of operation, refer to the State Diagram shown on page 7 of this data sheet. The IR2161 under voltage lock-out is designed to maintain an ultra low supply current of less than 300uA, and to guarantee the IC is fully functional before the high and low side output drivers are activated. Figure 1 shows a simple VCC supply arrangement that will work effectively, also when the convertor is being dimmed from a conventional triac based wall dimmer
be rated at 1.3W). The resistor RD in series with CD is necessary if the convertor is required to operate from a triac based (leading edge) phase cut dimmer. When the triac fires at a point during the mains half-cycle the high dv/ dt allows a large current to flow through this path to instantly charge CVCC to the maximum Vcc voltage. The external zener (DZ) will prevent possible damage to the IC by shunting excess current to COM. Once the capacitor voltage on VCC reaches the start-up threshold the IC turns on and HO and LO begin to oscillate. The supply resistor (RS) and RD/CD must be selected such that enough supply current is available over all ballast operating conditions. A bootstrap diode (DB) and supply capacitor (CB) comprise the supply voltage for the high side driver circuitry. To guarantee that the high-side supply is charged up before the first pulse on pin HO, the first pulse from the output drivers comes from the LO pin. During under voltage lock-out mode, the high and low-side driver outputs HO and LO are both low.
RD RS BR CD DS DB
LF CVCC
VCC COM
1
8
VB HO VS LO CB
M1
IR2161
2 3 4
7 6 5
CF DZ
CSD CS
M2
Soft Start Mode
The soft start mode is defined as the state the IC at system switch on when the lamp filament is cold. As with any type of filament lamp, the Dichroic Halogen lamp has a positive temperature coefficient of resistance such that the cold resistance (at switch on when the lamp has been off long enough to cool) is much lower than the hot resistance when the lamp is running. This normally results in a high inrush current occurring at switch on. Under worst-case conditions this could potentially trigger the convertor's shut down circuit. To overcome this problem the IR2161 incorporates the soft start function. When the IC starts oscillating the frequency is initially very high (about 120kHz). This causes the output voltage of the convertor to be lower since the HF transformer in the system has a fixed primary leakage inductance that will present a higher impedance at higher frequency and thus allowing less AC voltage to appear across the primary. The reduced output voltage will naturally result in a reduced current in the lamp which eases the inrush current thus avoiding tripping of the shutdown circuit and will ease the stress on the lamp filament as well as reducing the current in the half bridge MOSFETs (M1 and M2). The frequency sweeps down gradually from 120kHz to the
RL CSD CCS RCS
OUTPUT
Figure 1, Halogen Convertor. The start-up capacitor (CVCC) is charged by current through supply resistor (RS) minus the start-up current drawn by the IC. This resistor is chosen to provide sufficient current to supply the IR2161 from the DC bus. In a Halogen convertor it is important to consider that the DC bus is completely unsmoothed and has a full wave rectified shape. CVCC should be large enough to hold the voltage at Vcc above the UVLO threshold for one half cycle of the line voltage as it will only be charged at the peak. A charge pump consisting of two diodes (DCP1 and DCP2) connected to CSNUB is recommended to supply VCC as this allows RS to be a large value since it is only needed at startup. IF RS is required to supply the circuit without a charge pump it needs to be a relatively low value and consequently dissipates 1 to 2W, which is undesirable. An external 16V zener diode DZ has been added to avoid the need for the internal zener to dissipate power (it should
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IR2161(S)
minimum frequency over a period of around 1s (assuming CSD=100nF). During this time the external capacitor at the CSD pin charges from 0V to 5V, controlling the oscillator frequency through the internal voltage controlled oscillator (VCO). The value of CSD will determine the duration of the soft start sweep. However, since it also governs the shut down circuit delays, the value should be kept at 100nF to achieve the datasheet operation
ISS
CSD 5V
Set Oscillator Range
Figure 4, Cold Lamp Inrush Current with Soft Start.
Run Mode (Voltage Compensation)
Figure 2, Halogen Convertor. It can be seen from Figure 2, that at switch on, the CSD capacitor is internally switched to the soft start circuit input. A current source charges CSD linearly to 5V over a period of 0.5s at which time the comparator output goes high. The PMOS switch opens and the ISS current source is disconnected from CSD. The comparator latches high at this point and this causes the oscillator range to change and the CSD capacitor to be disconnected from the soft start circuit and connected to the voltage compensation circuit. The latching comparator has a built in delay of at least 20uS in order to prevent false triggering caused by transients. When soft start is completed the system switches over to compensation mode. This function provides some regulation of the output voltage of the convertor from minimum to maximum load. In this type of system it is desirable that the voltage supplied to the lamp does not exceed a particular limit. If the lamp voltage becomes too high the temperature of the filament runs too high and the life of the lamp is significantly reduced. The problem is that the output transformer is never perfectly coupled so there will always be a degree of load regulation. The transformer has to be designed such that the lamp voltage at maximum load is sufficiently high to ensure adequate light output. At minimum load the voltage will consequently be higher and is likely to exceed the maximum desired lamp voltage. In the widely used self-oscillating system based around bipolar power transistors, there is some frequency change (increasing the frequency reduces the output voltage) depending on the load that helps to compensate for this, although this is non-linear and depends on many parameters in the circuit and so is not easy to predict. The IR2161 based system includes a function that monitors the load current through the current sense resistor (RCS). The peak current is detected and amplified within the IC then appears at the CSD pin during run mode. The voltage
Figure 3, Typical Cold Lamp Inrush Current.
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IR2161(S)
ADVANCE DATA
across the CSD capacitor will vary from 0V if there is no load to approximately 5V at maximum load. This is provided that the correct value of current sense resistor has been selected for the maximum rated load and line voltage supply of the convertor. This should be 0.33 Ohm (0.5W) for a 100W system running from a 220-240V AC line. (It should be noted that the RCS resistor value is also critical for setting the limits for the shut down circuit) In RUN mode the oscillator frequency will vary from approximately 30kHz when VCSD is 5V (maximum load) to 55kHz when VCSD is 0V (no load). The result of this is that if a lighter load, such as a single 35W lamp, is connected to a 100W convertor, the frequency will shift upwards so that the output voltage falls below the maximum that is desirable for the lamp. This provides sufficient compensation for the load to ensure that the lamp voltage will always be within acceptable limits but does not require a complicated regulation scheme involving feedback from the output. An additional internal current source has been included to discharge the external capacitor. This will provide approximately 10% ripple at twice the line frequency if CSD is 100nF. The advantage of this is that during the line voltage half cycle the oscillator frequency will vary by several kHz thus spreading the EMI conducted and radiated emissions over a range of frequencies and avoiding high amplitude peaks at particular frequencies. In this way the filter components used may be similar to those used in a common bipolar selfoscillating system.
Figure 6, VS voltage and CSD voltage. In the above trace it can be seen that a leading edge phase cut (triac) dimmer is connected at close to maximum brightness. There is a short delay at the beginning of each half cycle before the AC line voltage is switched to the convertor. Dimming increases the ripple in the CSD voltage and gives more modulation. This is an inherent effect that causes no system problems. The startup sequence of the CSD pin can be seen from the point where VCC increases above the UVLO+ threshold.
AV > 13 CS CSD
12K
150K
Figure 5, Voltage Compensation Circuit Figure 7, Startup sequence of CSD.
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ADVANCE DATA
IR2161(S)
This trace shows that after the CSD voltage has ramped up through soft start, the system switches over to voltage compensation mode and a ripple exists which allows the frequency modulation (or "dither") to occur. In this case the convertor is close to maximum load. If the load is reduced, the average level at which the ripple occurs (i.e. the DC component) will be at a lower level.
I_SC CS 1.0V Shutdown Function I_OL
S 12V R
Q Q Enable Outputs
2.5V Switch CSD
0.5V Overload Function 4V I_RESET
Shut Down Circuit
The IR2161 contains a dual mode auto-resetting shutdown circuit that detects both a short circuit or overload condition in the convertor. The load current detected at the CS pin is used to sense these conditions. If the output of the convertor is short-circuited, a very high current will flow in the half bridge and the system must shut down within a few mains half cycles, otherwise the MOSFETs will rapidly be destroyed due to excessive junction temperature. The CS pin has an internal threshold of 1.2V so that if the voltage exceeds this level for more than 50mS, the system will shut down. A delay is included to prevent false tripping either due to lamp inrush current at switch on (this current is still higher than normal with the soft start operation) or transient currents that may occur if an external triac based phase cut dimmer is being used. There also exists a lower threshold of 0.5V, which has a much longer delay before it shuts down the system. This provides the overload protection if an excessive number of lamps is connected to the output or the output is shortcircuited at the end of a length of cable that has sufficient resistance to prevent the current from being large enough to trip the short circuit protection. Also under this condition there is an excessive current in the half bridge that is sufficient to cause heating and eventual failure but over a longer period of time. The threshold for overload shutdown is approximately 50% above maximum load with a delay of approximately 0.5s. These timings are based on a current waveform that has a sinusoidal envelope and a high frequency square wave component with 50% duty cycle. Both shutdown modes are auto resetting, which allows the oscillator to start again approximately 1.5s after shutting down. This is so that if the fault condition is removed the system can start operating normally again without the line voltage having to be switched off and back on again. It also provides a good indication of overload to the end user as all the lamps connected to the system will flash on and off continuously if too many are connected.
Figure 8, Shut Down Circuit. The shut down circuit also uses the external CSD capacitor for it's timing functions. When the 0.5V threshold is exceeded at CS the CSD is internally disconnected from the voltage compensation circuit and connected to the shutdown circuit. The oscillator operates at minimum frequency when the CSD capacitor is required for shutdown circuit timing. During soft start or run mode, if the 0.5V threshold is exceeded the IR2161 charges CSD rapidly to approximately 4V. While the CSD capacitor is being used by the shutdown circuit the oscillator frequency will default to minimum When the voltage at the CS input is greater than 0.5V, the CSD capacitor is charged by current source I_OL and when the short circuit threshold of 1.2V is exceeded it is charged by I_SC as well. If 1.2V is exceeded CSD will charge from 4V to 12V in approximately 50ms. When 0.5V is exceeded but 1.2V is not, CSD charges from 4V to 12V in approximately 0.5s. It should be remembered that, the timing accounts for the fact that high frequency pulses with approximately 50% duty cycle and a sinusoidal envelope appear at the CS pin. The values of I_SC and I_OL take into account that only at the peak of the mains will the comparator outputs go high and effectively the capacitor will be charged in steps each line half cycle. If a fault is detected but goes away before CSD reaches 12V, then CSD will discharge to 2.5V and then the system will revert to compensation mode without interruption of the output. Following a shutdown, when the system starts up again after the delay, the CSD capacitor will be internally switched back to the voltage compensation circuit. However, if the fault is still present the system will switch CSD back to the shutdown circuit again.
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IR2161(S)
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In addition, any time Vcs exceeds VCSLATCH (approximately half Vcc), this latching shutdown function will be triggered and the system will remain in FAULT mode until VCC is re-cycled. The IR2161 also includes over temperature shutdown, which latches the convertor off when the die temperature of the IC exceeds 130-140C. Experimantal measurement reveal that the die temperature will be no more than 20C above the ambient temperature at all operating frequencies inside the convertor.
Calculating Rcs
Figure 9, Short Circuit Output Current. The value of the current sense resistor Rcs is critical to achieve correct operation in the IR2161 based Halogen convertor.
DC Bus Voltage
VS LOAD VCSpk VCS RCS
Figure 10, Overload Output Current. In figures 9 and 10, trace (1) shows the half bridge oscillations during both types of fault mode and trace (2) shows the charging and discharging of the CSD capacitor. The IR2161 can also be externally shut off by applying a voltage above 0.5*Vcc to the CS pin. This will cause the system to go directly to a latched fault mode, after a delay of approximately 1uS to avoid the possibility of false tripping caused by transients. To restart the system, it is necessary to cycle Vcc off and on.
1/2 DC Bus Voltage
Figure 11, Calculating RCS Ignoring the output transformer we can assume for this calculation that the load is connected from the half bridge to the mid point of the two output capacitors and that the voltage at this point will be half the DC bus voltage. The RMS voltage of the DC bus is the same as that of the AC line so we can see that the RMS voltage across the load shown in Figure 8, will be half the RMS voltage of the line. The load is the maximum rated load of the convertor. The current in Rcs will be half the load current given by :
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IR2161(S)
I CS ( RMS )
P = LOAD VAC
In this case :
Since the load is resistive the current waveform will have a sinusoidal envelope and so the peak can be easily determined taking into account that the current has a high frequency component with an approximate 50% duty cycle:
100 x 0.33 = 0.062W 230
It is important to bear in mind that the resistor must be rated to handle this current in a high ambient temperature. IMPORTANT NOTE The filter resistor RL should be 1K, which is needed to protect the CS input from negative going transients. CCS should be 1nF and is also necessary to filter out switching transients that can impair the operation of the shutdown circuit.
2
I CS ( PK ) = 2 2 x I CS ( RMS )
Therefore:
VCS ( PK ) = I CS ( PK ) x RCS
For correct operation at maximum load the peak voltage should be 0.4V. The calculation can be simplified by combining the formulae,
Adaptive Dead Time
Because of the fact that the DC bus voltage varies during the mains half cycle, the dead time may need to vary in order to achieve soft switching. The IR2161 has an adaptive dead time circuit (ADT) that detects the point at which the voltage at the half bridge slews to 0V (COM) and sets the LO output high at this point. There is an internal sample and hold system that allows approximately the same delay to be used to set HO high after LO has gone low. This reacts on a cycle-by-cycle basis of the oscillator and therefore will adjust the dead time as necessary regardless of external conditions.
RCS =
0.4 VCS 2 2 PLOAD VAC PLOAD
Which can be simplified to:
RCS = 0.141
Example
For a 100W convertor working from a 230VAC supply the current sense resistor would need to be :
0.141x 230 = 0.324 100
The nearest preferred value to this would be 0.33 Ohms. The power dissipation in Rcs should also be considered and is given by :
P PCS = LOAD VAC
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x RCS
2
Figure 12, ADT when VS slews from VBUS to COM
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of the power MOSFETs in the half-bridge will be at a maximum. At lighter loads there may be hard switching if the VS voltage is unable to slew all the way or it slews so rapidly that the voltage begins to turn around again before the IR2161 is able to switch on the relevant MOSFET in the half bridge. Such a situation is not desirable but may be acceptable at lighter loads where the conduction losses are small. With correct optimization of the output transformer and surrounding circuit it is possible to achieve a design that will not hard switch from 20% to 100% of the maximum rated load of the system. This system avoids the need for an external resistor to program the dead time and contributes to the multi functional nature of the CSD pin to the IR2161 being realized with only 8 external pins In any design when there is no load at the output, the VS voltage will not slew and obviously the ADT circuit is not able to function in this condition. In this case the dead time will default to approximately 1.2uS, the maximum allowed by the IC and there will be hard switching. Although this will inevitably lead to some switching losses, there are no conduction losses so the temperature rise of the half bridge MOSFETs should not create a problem in this case.
Figure 13, ADT when VS slews from COM to VBUS The above waveforms are typical, showing the operation of the ADT circuit in either direction. In this case the design could be optimized further by increasing the snubber capacitor to slightly increase the slew time, in order to account for the propagation delays in the system. Alternatively an output transformer with a greater leakage inductance can extend the period before the VS voltage turns around and starts to go back the other way again. The designer does not need to take into account parasitic capacitances in the MOSFETs or leakage inductance in the output transformer and fix the dead time accordingly. The system can operate reliably down to dead times in the order of 300nS, which should be low enough to accommodate the output transformer leakage inductance and parasitic MOSFET capacitances of a practical Halogen convertor. The slew rate can easily be increased, if necessary, by adding a small snubber capacitor across the primary of the transformer if necessary. However, should the snubber capacitor be too large, it will prevent the VS voltage from slewing all the way to the opposite rail. Consequently the ADT function will be unable to operate, causing the IR2161 to revert to the default dead time of 1.2 to 1.4uS. Snubber capacitors would normally be in the order of hundreds of pF. When designing a halogen convertor it is desirable to optimize the system at maximum load, where the conduction losses
Dimming
Almost any Halogen convertor available can be dimmed by an external phase cut dimmer that operates in trailing edge mode. This means that at the beginning of the line voltage half cycle, the switch inside the dimmer is closed and mains voltage is supplied to the convertor allowing the convertor to operate normally. At some point during the half cycle, the switch inside the dimmer is opened and voltage is no longer applied. The DC bus inside the convertor almost immediately drops to 0V and the output is no longer present. In this way bursts of high frequency output voltage are applied to the lamp. The RMS voltage across the lamp will naturally vary depending on the phase angle at which the dimmer switch switches off. In this way the lamp brightness may easily be varied from zero to maximum output.
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ADVANCE DATA
IR2161(S)
DC BUS VOLTAGE
DC BUS VOLTAGE
LAMP VOLTAGE
LAMP VOLTAGE
Figure 14, Trailing Edge Dimming Trailing edge dimmers are less common however than leading edge dimmers. This is because they are more expensive to make and need to incorporate a pair of MOSFETs or IGBTs whereas a leading edge dimmer is based around a single triac. Conversely many Halogen convertors are not able to operate with leading edge dimmers because of the fact that they are based around a triac. It is possible, however, to design a Halogen convertor that will work effectively with a triac based dimmer by designing the input filter components correctly ensuring that at the firing point of the triac the oscillator can start up rapidly. In the IR2161 based system this is easy to achieve through the addition of RD and CD, which conduct a large current to VCC due to the high dv/dt that occurs when the triac fires. At the same time, the bus voltage rises rapidly from zero to the AC line voltage. If the VCC voltage falls below UVLO- during the time when the triac in the dimmer is off, the soft start will not be initiated because the soft start circuit is not reset until VCC drops approxmately 2V below UVLO-. This takes some time as the VCC capacitor discharges very slowly during UVLO micro-power operation. The intermediate period is referred to as Standby mode. During dimming the voltage compensation circuit will cause a frequency shift upward at angles above 90 because the peak voltage at CS will be reduced (see figure 15). This will result in a reduction of voltage at CSD and thus an increase in frequency. However this will not have a noticeable effect on the light output. The problem associated with operation of Halogen convertors with triac dimmers is due to the fact that after a triac has been fired it will conduct until the current falls below its
Figure 15, Leading Edge Dimming holding current. If the load is purely resistive (as in a filament lamp directly connected to the dimmer) this will naturally happen at the end of the line voltage half cycle as the current has to fall to zero. In a Halogen convertor it is necessary to place a capacitor and inductor at the AC input to comply with regulations regarding EMI conducted emissions. This means that when the line voltage falls to zero there could still be some current flowing that is enough to keep the triac switched on and so the next cycle will follow through and not be phase cut as required. This can happen intermittently resulting in flickering of the lamps. The way to avoid the problem is to ensure that the product has the smallest possible filter capacitor CCS and to state a minimum load for the convertor. This would be typically one third of the maximum load to avoid problems of this kind.
Figure 15, Half Bridge voltage and current during dimming
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IR2161(S)
ADVANCE DATA
15
5
VCCUV+
12 4 IQCC (mA)
ICCHF
VCC(V)
9
VCCUV-
3
6
2
ICCLF
3
1
IQCCFLT
0 -25
0
25
50
75
100
125
0 -25
0
25
50
75
100
125
Temperature (C)
Temperature (C)
Graph : VCCUV+/- vs TEMP (IR2161)
Graph : IQCC vs TEMP (IR2161)
20
6
VCCLAMP_25ma
VCCLAMP_5_25ma 15
5 4 VCSD (V) 3 2
VCSDMAX
VCCLAMP_5ma
10
5 1
VCSDMIN
0 -25 0 25 50 75 100 125 0 -25 0 25 50 75 100 125
Temperature (C)
Temperature (C)
Graph : VCCLAMP_5_25ma vs TEMP (IR2161)
VCSDMIN,MAX vs TEMP (IR2161)
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ADVANCE DATA
IR2161(S)
2
20
VCSOL, VCSSC (V)
1.5
15
VCS_SC
I (uA) 1 10
I_OL
0.5
5
VCS_OL
I_RESET
0 -25 0 25 50 75 100 125 0 -25 0 25 50 75 100 125
Temperature (C)
Temperature (C)
VCS_OL, VCS_SC vs TEMP (IR2161)
I_RESET, I_OL vs TEMP (IR2161)
100
12
I_SC
90
VCSD_SD
9 VCSD (V)
I(uA)
80
6
VCSD_OL
3
70
VCSD_RS
60 -25 0 25 50 75 100 125
0 -25
0
25
50
75
100
125
Tem perature (C)
Temperature (C)
I_SC vs TEMP (IR2161)
Graph : VCSDSD,OL,RS vs TEMP (IR2161)
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17
IR2161(S)
ADVANCE DATA
175 150 125 100 75 50
1
FSS
Iss (uA)
0.8
Frequency (kHz)
0.6
FRUN
0.4
0.2 25 0 -25
FMIN
0 25 50 75 100 125 0 -25 0 25 50 75 100 125
Temperature (C)
Temperature (C)
Frequency vs TEMP (IR2161)
Graph : Iss (uA) vs TEMP (IR2161)
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ADVANCE DATA
IR2161(S)
Case outlines
IR2161 8-Lead PDIP
D A 5 B
FOOTPRINT 8X 0.72 [.028]
01-6014 01-3003 01 (MS-001AB)
DIM A b c D INCHES MIN .0532 .013 .0075 .189 .1497 MAX .0688 .0098 .020 .0098 .1968 .1574 MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00
A1 .0040
6 E
8
7
6
5 H 0.25 [.010] A
E
6.46 [.255]
1
2
3
4
e e1 H K L
8X 1.78 [.070]
.050 BASIC .025 BASIC .2284 .0099 .016 0 .2440 .0196 .050 8
1.27 BASIC 0.635 BASIC 5.80 0.25 0.40 0 6.20 0.50 1.27 8
6X
e e1
3X 1.27 [.050]
y
A C 0.10 [.004] y
K x 45
8X b 0.25 [.010]
NOTES:
A1 CAB
8X L 7
8X c
1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994. 2. CONTROLLING DIMENSION: MILLIMETER 3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES]. 4. OUTLINE C ONFORMS TO JEDEC OUTLINE MS-012AA.
5 DIMENSION DOES NOT INC LUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006]. 6 DIMENSION DOES NOT INC LUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010]. 7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO A SUBSTRATE.
IR2161S
8-Lead SOIC
01-6027 01-0021 11 (MS-012AA)
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. 3/12/2004
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